In semiconductor process development, it is usually required wafer acceptance test (WAT) at a lower level metal layer (such as the 1st or 2nd level metal layer) to have quick feedback on both device performance and process margin. However, this will face a test robustness problem when the technology and metal pitcher continuously scale down to smaller feature sizes in advanced technology nodes. Therefore it requires the metal thickness (depth) thinner to maintain metal trench aspect ratio (depth/width) to have enough process margins for various fabrication processes (such as etching and metal deposition) during the formation of the corresponding metal layer. For example, during the formation of metal lines in this metal layer by a damascene process, it is challenge to etch an interlayer dielectric material to form trenches and vias with high aspect ratios when the metal layer is thick. Furthermore, it is challenge to deposit a metal in the trenches and/vias with high aspect ratio. On other side, a thinner metal layer easily causes WAT test failure due to various factors, such as high contact resistance or open, or probe punching through the test pads. Thinner metal layer is also conflicted with lower level metal test requirement.
Packing density is also a challenge when the semiconductor is scaled down to small feature sizes. For example, a logic circuit includes various logic gates, such as inverters, NAND gates, AND gates, NOR gates and flip-flop. In deep sub-micron integrated circuit technology, the logic circuit progressed to smaller feature sizes for higher packing density. However, the existing structure of a logic circuit still has various aspects to be improved for its performance and further enhanced packing density.
It is therefore desired to have an integrated circuit design and structure, and the method making the same to address the above issues with increased packing density.